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si9166 vishay siliconix document number: 70847 s-40701?rev. c, 19-apr-04 www.vishay.com 1 high frequency programmable topology controller features buck or boost configuration voltage mode control 2.7-v to 6-v input voltage range for v dd and v s programmable pwm/psm control ? up to 2-mhz switching frequency in pwm ? synchronous rectification in pwm ? less than 200- a i dd in psm integrated uvlo and por integrated soft-start synchronization shutdown current <1 a description the si9166 is a programmable topology controller for today?s continuous changing portable electronic market. si9166 provides flexibility of utilizing various battery configurations and chemistries such as nicd, nimhy, or li+ with input voltage range of 2.7 v to 6 v. an additional flexibility is provided with topology programmability to power multiple loads such as power amplifiers, microcontrollers, or baseband logic ic?s. the converters can be programmed to be synchronous buck or boost topology. for ultra-high efficiency, converters are designed to operate in synchronous rectified pwm mode under full load while transforming into externally controlled pulse skipping mode (psm) under light load. all these features are provided by the si9166 without sacrificing system integration requirements of fitting these circuits into ever demanding smaller and smaller space . the si9166 is capable of switching up to 2 mhz to minimize the output inductor and capacitor size in order to decrease the overall converter size. the si9166 is available in both standard and lead (pb)-free tssop-16 pin packages and specified to operate over the industrial temperature range of ? 25 c to 85 c. typical application circuits boost configuration buck configuration v s mode n/c sd dh dl pwm/psm pgnd sync v o gnd v dd ref r osc fb comp dd s 1 s 2 s 1 s 2 g 1 g 2 si6803 si9166 v out v in sd n/c pwm/psm sync v s mode n/c sd dh dl pwm/psm pgnd sync v o gnd v dd ref r osc fb comp dd s 1 s 2 s 1 s 2 g 1 g 2 si6803 si9166 v out v in sd n/c pwm/psm sync
si9166 vishay siliconix www.vishay.com 2 document number: 70847 s-40701?rev. c, 19-apr-04 absolute maximum ratings voltages referenced to gnd v dd 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode, pwm/psm , sync, sd , v ref , r osc comp, fb ? 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v o ? 0.3 v to v s + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pgnd 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltages referenced to pgnd v s. 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dh, dl ? 0.3 v to v s + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak output current (dh, dl) 1.5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) a 16-pin tssop (q suffix) b 925 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) 16-pin tssop 135 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. b. derate 7.4 mw/ c above 25 c. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions voltages referenced to agnd v dd 2.7 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode, pwm/psm , sync, sd 0 v to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltages referenced to pgnd v s 2.7 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f osc 200 khz to 2 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r osc 25 k to 300 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ref capacitor 0.1 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . specifications test conditions unless otherwise specified limits parameter symbol unless other w ise specified 2.7 v v dd , v s 6 v min a typ b max a unit reference output voltage v ref i ref = 0a 1.268 1.3 1.332 v output voltage v ref i ref = 0, t a = 25 c 1.280 1.3 1.320 v load regulation v ref v dd = 3.3 v, ? 500 a < i ref <0 3 mv power supply rejection p srr 60 db uvlo under voltage lockout (turn-on) v uvlolh 2.3 2.4 2.5 v hysteresis v hys v uvlolh ? v uvlohl 0.1 v soft-start tim ss time tss 6 ms mode logic high v ih 0.7 v dd v logic low v il 0.3 v dd v input current i l ? 1.0 1.0 a sd , sync, pwm/psm logic high v ih 2.4 v logic low v il 0.8 v input current i l ? 1.0 1.0 a
si9166 vishay siliconix document number: 70847 s-40701?rev. c, 19-apr-04 www.vishay.com 3 specifications limits test conditions unless otherwise specified 2.7 v v dd , v s 6 v parameter unit max a typ b min a test conditions unless otherwise specified 2.7 v v dd , v s 6 v symbol oscillator maximum frequency f osc 2 mhz accuracy nominal 1.60 mhz, r osc = 30 k ? 20 20 maximum duty cycle?buck d max f sw = 2 mhz (non ldo mode) 75 85 % maximum duty cycle?boost d max f sw = 2 mhz 52 65 sync range f sync /f osc 1.2 1.5 sync low pulse width 50 sync high pulse width 50 ns sync t r , t f 50 error amplifier input bias current i bias v fb = 1.4 v ? 1 1 a open loop voltage gain a vol 50 60 db fb threshold v fb t a = 25 c 1.270 1.30 1.330 v fb threshold v fb 1.258 1.30 1.342 v unity gain bw bw 2 mhz output current i ea source (v fb = 1.05 v), v comp = 0.75 v ? 3 ? 1 ma output current i ea sink (v fb = 1.55 v), v comp = 0.75 v 1 3 ma power supply rejection psrr 60 db output drive ( dh and dl) output high v oltage v oh v s = 3.3 v, i out = ? 20 ma 3.18 3.24 v output low voltage v ol v s = 3.3 v, i out = 20 ma 0.06 0.12 v peak output source i source v s = 3 3 v dh = dl = v s /2 ? 750 ? 500 ma peak output sink i sink v s = 3.3 v, dh = dl = v s /2 500 750 ma break-before-make t bbm v s = v dd = 3.3 v 30 ns supply normal mode v dd = 3.3 v, f osc = 2 mhz 500 750 psm mode i dd v dd = 3.3 v 180 250 a shutdown mode v dd = 3.3 v, sd = 0 v 1 notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. typical values are for design aid only, not guaranteed nor subject to production testing.
si9166 vishay siliconix www.vishay.com 4 document number: 70847 s-40701?rev. c, 19-apr-04 typical characteristics (25 c unless otherwise noted) 1 10 1000 100 buck mode efficiency, v o = 2.7 v 1.70 1.75 1.80 1.85 1.90 1.95 2.00 ? 100 ? 50 0 50 100 150 100 1000 10000 10 100 1000 frequency vs. t emperature r osc (k ) frequency (mhz) temperature ( c) frequency vs. r osc frequency (khz) 1.28 1.29 1.30 1.31 1.32 ? 50 0 50 100 150 v ref vs. t emperature temperature ( c) (v) v ref 1.290 1.295 1.300 1.305 1.310 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v ref vs. v dd v dd ? (v) (v) v ref boost mode efficiency, v o = 3.6 v 50 100 60 70 effocoemcu (%) load current (ma) 80 90 1 50 100 60 70 10 1000 effocoemcu (%) load current (ma) 80 90 100 psm ? 3 v psm ? 3.3 v pwm ? 3 v pwm ? 3.6 v pwm ? 3.3 v psm ? 3.6 v psm ? 2.7 v psm ? 3 v pwm ? 3.3 v r osc = 25 k psm ? 3.3 v pwm ? 3 v pwm ? 2.7 v
16 15 14 13 1 2 3 4 12 11 10 9 5 6 7 8 v s mode n/c sd dh dl pwm/psm pgnd sync v o gnd v dd v ref r osc fb comp tssop-16 top view si9166 vishay siliconix document number: 70847 s-40701?rev. c, 19-apr-04 www.vishay.com 5 typical characteristics (25 c unless otherwise noted) 50 100 150 200 250 234567 200 300 400 500 600 700 800 234567 pwm supply current psm supply current v dd ? (v) v dd ? (v) (ma) i dd (ma) i dd pin configuration ordering information part number temperature range package si9166bq-t1 25 to 85 c tape and reel si9166bq-t1?e3 ? 25 to 85 c tape and reel eval kit temperature range board type si9166db ? 25 to 85 c surface mount pin description pin symbol description 1 v s input supply voltage for the output driver section. input voltage range is 2.7 v to 6v 2 n/c not used 3 dh the gate drive output for the high-side p-channel mosfet. the p-channel mosfet is the main switch for buck topology and the synchronous rectifier for the boost topology. 4 pwm/psm logic high = pwm mode, logic low = psm mode. in psm mode, synchronous rectification is disabled. 5 sync externally controlled synchronization signal. logic high to low transition forces the clock synchronization. if not used, the pin must be connected to v dd , or logic high. 6 gnd low power controller ground 7 v ref 1.3-v reference. decoupled with 0.1- f capacitor 8 fb output voltage feedback connected to the inverting input of an error amplifier. 9 comp error amplifier output for external compensation network. 10 r osc external resistor to determine the switching frequency. 11 v dd input supply voltage for the analog circuit. input voltage range is 2.7 v to 6 v. 12 v o direct output voltage sense 13 pgnd power ground for output drive stage 14 dl the gate drive output for the low-side n-channel mosfet. the n-channel mosfet is the synchronous rectifier for the buck topology and the main switch for the boost topology. 15 sd shuts down the ic completely and decreases current consumed by the ic to < 1 a. 16 mode determines the converter topology. connect to agnd for buck or v dd for boost.
si9166 vishay siliconix www.vishay.com 6 document number: 70847 s-40701?rev. c, 19-apr-04 functional block diagram reference threshold generator oscillator psm modulator pwm modulator soft-start timer uvlo por bias generator drivers pwm/psm select v dd sd gnd pgnd positive supply negative return and substrate pwm en psm en pwm in psm in 0.5 v 1.0 v ramp c osc v ref v o fb comp sync r osc pwm/psm mode dl dh v s system monitor 1.3 v detail operational description start-up the uvlo circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on v dd pin is less than 2.5 v. with typical uvlo hysteresis of 0.1 v, controller is continuously powered on until the v dd voltage drops below 2.4 v. this hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. once the v dd voltage exceeds the uvlo threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. after the por time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. when the soft-start capacitor voltage reaches 0.5 v, the pwm circuit is enabled. thereafter, the constant current charging the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. to prevent negative undershoot, the synchronous switch is tri-stated until the duty cycle reaches about 10%. see start-up timing diagram. in tri-state, the high-side p-channel mosfet is turned off by pulling up the gate voltage (dh) to v s potential. the low-side n-channel mosfet is turned off by pulling down the gate voltage (dl) to pgnd potential. note that the si9166 will always soft start in the pwm mode regardless of the voltage level on the pwm/psm pin. shutdown the si9166 is designed to conserve battery life by decreasing current consumption of ic during normal operation as well as the shutdown mode. with logic low-level on the sd pin, current consumption of the si9166 decreases to less than 1 a by shutting off most of the circuits. the logic high enables the controller and starts up as described in start-up section above. mode selection the si9166 can be programmed to operate as buck or boost converter. if the mode pin is connected to agnd, it operates in buck mode. if the mode pin is connected to v dd , it operates in boost mode. the dh gate drive output is designed to drive high-side p-channel mosfet, acting as the main switch in buck topology and the synchronous rectifier in boost topology. the dl gate drive output is designed to drive low-side n-channel mosfet, acting as the synchronous rectifier in buck topology and the main switch in boost topology.
si9166 vishay siliconix document number: 70847 s-40701?rev. c, 19-apr-04 www.vishay.com 7 pwm mode with pwm/psm mode pin in logic high condition, the si9166 operates in constant frequency (pwm) mode. as the load and line varies, switching frequency remain constant. the switching frequency is programmed by the r osc value. in the pwm mode, the synchronous drive is always enabled, even when the output current reaches 0 a. therefore, the converter always operates in continuous conduction mode (ccm) if a synchronous switch is used. in ccm, transfer function of the converter remains almost constant, providing fast transient response. if the converter operates in discontinuous conduction mode (dcm), overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. this transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc/dc converter to meet the transient voltage regulation. the pwm/psm pin is available to dynamically program the controller. if the synchronous rectifier switch is not used, the converter will operate in dcm at light load. the maximum duty cycle of the si9166 can reach 100% in buck mode. the duty cycle will continue to increase as the input voltage decreases until it reaches 100%. this allows the system designers to extract the maximum stored energy from the battery. once the controller delivers 100% duty cycle, the converter operates like a saturated linear regulator. at 100% duty cycle, synchronous rectification is completely turned off. up to 80% maximum duty cycle at 2-mhz switching frequency, the controller maintains perfect output voltage regulation. if the input voltage drops below the level where the converter requires greater than 80% duty cycle, the controller will deliver 100% duty cycle. this instantaneous jump in duty cycle is due to fixed bbm time, mosfet delay/rise/fall time, and the internal propagational delays. in order to maintain regulation, controller might fluctuate its duty cycle back and forth from 100% to something lower than 80% while the converter is operating in this input voltage range. if the input voltage drops further, controller will remain on 100%. if the input voltage increases to a point where it?s requiring less than 80% duty cycle, synchronous rectification is once again activated. the maximum duty cycle under boost mode is internally limited to 70% to prevent inductor saturation. if the converter is turned on for 100% duty cycle, inductor never gets a chance to discharge its energy and eventually saturate. in boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. the controller will deliver 0% duty cycle, if the input voltage is greater than the programmed output voltage. because of signal propagation time and mosfet delay/rise/fall time, controller will not transition smoothly from minimum controllable duty cycle to 0% duty cycle. for example, controller may decrease its duty cycle from 5% to 0% abruptly, instead of gradual decrease you see from 70% to 5%. pulse skipping mode the gate charge losses produced from the miller capacitance of mosfets are the dominant power dissipation parameter during light load (i.e. < 10 ma). therefore, less gate switching will improve overall converter efficiency. this is exactly why the si9166 is designed with pulse skipping mode. if the pwm/psm pin is connected to logic low level, converter operates in pulse skipping modulation (psm) mode. during the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 a, instead of 500 a during the pwm mode. this is accomplished by turning off most of internal control circuitry and utilizing a simple constant on-time control with feedback comparator. the controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. if the output voltage drops below the desired level, the main switch is first turned on and then off. if the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. if the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. the excess energy is delivere d to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. the on-time and off-time are set internally based on inductor used (1.5- h typical), mode pin selection and maximum load current. therefore, with this control method, duty cycle ranging from 0 to near 100% is possible depending on whether buck or boost is chosen. in pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss and increase overall converter efficiency. reference the reference voltage for the si9166 is set at 1.3 v. the reference voltage is internally connected to the non-inverting inputs of the error amplifier. the reference pin requires 0.1- f decoupling capacitor. error amplifier the error amplifier gain-bandwidth product and slew rate are critical parameters which determines the transient response of converter. the transient response is function of both small and large signal responses. the small signal response is determined by the feedback compensation network while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. besides the inductance value, error amplifier determines the converter response time. in order to minimize the response time, the si9166 is designed with 2-mhz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 v/ sec slew rate for ultra-fast large signal response.
si9166 vishay siliconix www.vishay.com 8 document number: 70847 s-40701?rev. c, 19-apr-04 oscillator the oscillator is designed to operate up to 2-mhz minimal. the 2-mhz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. even with 2-mhz switching frequency, quiescent current is only 500 a with unique power saving circuit design. the switching frequency is easily programmed by attaching resistor to r osc pin. see oscillator frequency versus r osc curve to select the proper timing values for desired operating frequency. the tolerance on the operating frequency is (20% with 1% tolerance resistor). synchronization the synchronization to external clock is easily accomplished by connecting the external clock into the sync pin. the logic high-to-low transition synchronizes the clock. the external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. break-before-make timing a proper bbm time is essential in order to prevent shoot-through current and to maintain high efficiency. the break-before-make time is set internally at 20 to 60 ns @ v s = 3.6 v. the high- and low-side gate drive voltages are monitored and when the gate to source voltage reaches 1.75 v above or below the initial starting voltage, 20 to 60 ns bbm time is set before the other gate drive transitions to its proper state. the maximum and minimum duty cycle is limited by the bbm time. since the bbm time is fixed, controllable maximum duty cycle will vary depending on the switching frequency. output driver stage the dh pin is designed to drive the high-side p-channel mosfet, independent of topology. the dl pin is designed to drive the low-side n-channel mosfet, independent of topology. the driver stage is sized to sink and source peak currents up to 450 ma with v s = 3.3 v. the ringing from the gate drive output trace inductance can produce negative voltage on the dh and dl respect to pgnd. the gate drive circuit is capable of withstanding these negative voltages without any functional defects.
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.
vishay siliconix package information document number: 74417 23-oct-06 www.vishay.com 1 symbols dimensions in millimeters min nom max a - 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.22 0.28 0.38 c - 0.127 - d 4.90 5.00 5.10 e 6.10 6.40 6.70 e1 4.30 4.40 4.50 e-0.65- l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y--0.10 1036 ecn: s-61920-rev. d, 23-oct-06 dwg: 5624 tssop: 16-lead
pad pattern www.vishay.com vishay siliconix revision: 02-sep-11 1 document number: 63550 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended minimum pad for tssop-16 0.281 (7.15) recommended minimum pads dimensions in inches (mm) 0.171 (4.35) 0.055 (1.40) 0.012 (0.30) 0.026 (0.65) 0.014 (0.35) 0.193 (4.90)
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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